ForthereliabilityandpowerconsumptionissuesofEthernetdatatransmissionbasedonthefieldprogrammablegatearray(FPGA),alow-powerconsumptiondesignmethodisproposed,whichissuitableforFPGAimplementation.Toreducethedynamicpowerconsumptionofintegratedcircuit(IC)design,theproposedmethodadoptsthedynamiccontroloftheclockfrequency.Formostofthetime,whentheportisintheidlestateorlower-ratestate,userscanreduceoreventurnoffthereadingclockfrequencyandreducetheclockflipfrequencyinordertoreducethedynamicpowerconsumption.Whenthereceivingrateishigh,thereadingclockfrequencywillbeimprovedtimelytoensurethatnodatawilllost.SimulatedandverifiedbyModelsim,theproposedmethodcandynamicallycontroltheclockfrequency,includingthedynamicswitchingofhigh-speedandlow-speedclockfliprates,orstopoftheclockflip.
