简介:Aradiationhardphase-lockedloop(PLL)isdesignedat2.5GHzusingsilicononsapphirecomplementarymetal-oxide-semiconductorprocess.Radiationhardnessisachievedthroughimprovingcircuitdesignwithoutsacrificingrealestate.Stabilityisguaranteedbyafullyself-biasarchitecture.ThelocktimeofPLLisminimizedbymaximizingtheloopbandwidth.Frequencytuningrangeofvoltagecontrolledoscillatorissignificantlyenhancedbyanovelloadconfiguration.Inaddition,multiplebiasstages,asynchronousfrequencydivider,andsilicononsapphireprocessjointlymaketheproposedPLLmoreradiationhard.LayoutofthisPLLissimulatedbyCadenceSpectreRFunderbothsingleeventeffectandtotalinduceddoseeffect.Simulationresultsdemonstrateexcellentstability,locktime<600ns,frequencytuningrange[1.57GHz,3.46GHz],andjitter<12ps.ThroughcomparisonwithPLLsinliteratures,thePLLisespeciallysuperiorintermsoflocktimeandfrequencytuningrangeperformances.
简介:有非线性赔偿的一个高速度列平行CDS/ADC电路在这份报纸被建议。相关双采样(CDS)和analog-to-digital变换器(模数转换器)工作基于二漂浮门inverters和开关电容器网络集成于一个三阶段的列平行电路。传统的单个斜坡的模数转换器的变换率被划分量子化到粗糙的步和好步加快。一个存储电容器被用来存储粗糙的步的结果并且定位好步的斜面信号的节,它能从2n把钟步骤归结为2(n/2+1)。漂浮的门inverters被实现减少电源消费。它的导致的非线性的偏移量被把一个赔偿模块介绍给inverter的输入取消,它能在建议电路的三个阶段使相等联合路径。这个电路与640为互补金属氧化物半导体图象传感器被设计并且模仿,
简介:AwedgeshapeSiLEDisdesignedandfabricatedwith0.35μmdouble-gratingstandardCMOStechnology.ThedevicestructureisbasedontheN-well-P+junction.TheP+hasawedgeshapeandissurroundedbytheN-well.ThemicrographsofSiLEDs'emittingandlayoutarecaptured.TheI-VcharacteristicandspectraoftheSiLEDaretested.Underroomtemperatureandbackwardbias,itsradiantluminosityis12nWat100mA,andthewavelengthoftheemittingpeakislocatedat764nm.